1. Field of the Invention
The present invention relates to the field of non-volatile memory devices. More particularly, the invention relates to a method of erasing multi-bit flash electrically erasable programmable read only memory (EEPROM) cells that utilize the phenomena of hot electron injection to trap charge within a trapping dielectric material within the gate.
2. Discussion of Related Art
Memory devices for non-volatile storage of information are currently in widespread use today, being used in a myriad of applications. A few examples of non-volatile semiconductor memory include read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and flash EEPROM.
Semiconductor EEPROM devices involve more complex processing and testing procedures than ROM, but have the advantage of electrical programming and erasing. Using EEPROM devices in circuitry permits in-circuit erasing and reprogramming of the device, a feat not possible with conventional EPROM memory. Flash EEPROMs are similar to EEPROMs in that memory cells can be programmed (i.e., written) and erased electrically but with the additional ability of erasing all memory cells at once, hence the term flash EEPROM.
An example of a single transistor Oxide-Nitrogen-Oxide (ONO) EEPROM device is disclosed in the technical article entitled "A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device," T. Y. Chan, K. K. Young and Chenming Hu, IEEE Electron Device Letters, March 1987. The memory cell is programmed by hot electron injection and the injected charges are stored in the oxide-nitride-oxide (ONO) layer of the device. This article teaches programming and reading in the forward direction. Thus, a wider charge trapping region is required to achieve a sufficiently large difference in threshold voltages between programming and reading. This, however, makes it much more difficult to erase the device.
Erasure of EEPROM devices in general is disclosed in U.S. Pat. Nos. 5,077,691; 5,561,620; 5,598,369; 5,617,357; 5,708,588 and for ONO EEPROM devices is disclosed in both U.S. Pat. No. 5,768,192 and PCT patent application publication WO 99/07000, the contents of each reference identified above are hereby incorporated herein by reference. In those disclosed devices, a cell is erased by applying a negative voltage to the gate or a zero bias on the gate in conjunction with a large, positive bias on the drain over a plurality of cycles. As is well known, the degree of erasure or removal of charge from a cell of such devices is a strong function of both the vertical and lateral fields created in the cell. In particular, the lateral field creates hot carriers through impact ionization that are used to erase the charge in the cell. Obviously, the larger the number of hot carriers created by the lateral field, the faster the erasure process will proceed. In this case, the number of hot carriers created through impact ionization is directly proportional to the magnitude of the lateral field created in the cell. However, the negative bias between the gate and the drain also produces carriers through band-to-band tunneling that limit the effect of the hot carriers during the erasure cycle and so slow down the erasure process.